1. Field of the Invention
The present invention relates to SRAM (Static Random Access Memory) provided with memory cells each including 6 MOS (Metal Oxide Semiconductor) transistors (hereinafter referred to as full-CMOS cell) and a fabrication process therefor, and more particularly, to a structure of a SRAM memory cell capable of improving soft error resistance and a fabrication process therefor.
2. Description of the Background Art
In company with development toward a lower operating voltage in SRAM devices, the main stream in 3 volt or less applications, a few years ago, had been SRAMs with memory cells including 4 MOS transistors of a high resistance load type or a TFT load type and two loads.
However, with further progress in reduced operating voltage such as 2.5 V, 1.8 V and to 1.5 V in recent years, a need for SRAM devices of a high resistance load type or a TFT load type have been on the decline because of its poor operating characteristics and instead, the dominant place has been being occupied by SRAMs having full-CMOS cells each including 6 MOS transistors.
Note that the term xe2x80x9cfull-CMOS cellxe2x80x9d generally means a memory cell constructed of 2 bulk access n MOS transistors, 2 bulk driver n MOS transistors and 2 bulk load p MOS transistors.
A full-CMOS cell is superior to an SRAM cell of a high resistance load type or a TFT load type, both having storage nodes of a low charging ability, in regard to soft error resistance since in the full-CMOS cell, a storage node on the H (high) side of a bulk p MOS transistor can be charged. Note that soft errors are a phenomenon that xcex1 particle radiation emitted from radioactive impurities such as U or Th present in trace levels in common semiconductor packaging substances passes through a silicon substrate, and thereby, electron-hole pairs are generated in the bulk of the substrate and the information state of a cell is upset by noise of generated electron-hole pairs, leading to malfunction of the memory.
With progressive reduction in design rules, a cell size of SRAM memory has been smaller year by year and the trend toward lower operating voltage has also been enhanced. Along with such circumstances in change, a stored electric charge (voltage x capacitance) of a storage node of a SRAM memory cell has been on the decrease, which produces a soft error problem even in a full-CMOS cell.
For this reason, there has arisen a necessity to develop a method of protecting memory cells from soft errors even in a case of a full-CMOS cell, especially of a low operating voltage type adopting fine design rules of 0.18 xcexcm or less.
An example of a full-CMOS cell to which a capacitance is added for reducing a soft error rate is disclosed in U.S. Pat. No. 5,541,427, wherein a capacitance is formed on an interconnect connecting storage nodes therebetween.
In order to obtain the above described capacitance, in U.S. Pat. No. 5,541,427 an insulating layer and a metal layer such as of tungsten are formed on an interconnect connecting storage nodes therebetween. The insulating layer and the metal layer are patterned using respective different masks. Therefore, a case arises where a capacitance decreases and cannot be ensured to a desired level, due to poor registration between masks in fabrication process for the insulating layer and the metal layer.
The present invention has been made in order to solve the above problem. It is accordingly an object of the present invention is to reduce a variation in capacitance added to a storage node of a semiconductor memory device.
A semiconductor memory device includes: memory cells each having first and second access MOS transistors, first and second driver MOS transistors and first and second load MOS transistors; a first gate forming a gate of the first driver MOS transistor and a gate of the first load transistor; a first conductive layer, formed on the first gate with a first insulating layer interposing therebetween, and for forming a capacitance between the first gate and the first conductive layer; a second gate forming a gate of the second driver MOS transistor and a gate of the second load MOS transistor; a second conductive layer, formed on the second gate with a second insulating layer interposing therebetween, and for forming a capacitance between the second gate and the second conductive layer; a first local interconnect connecting the first gate and the second conductive layer therebetween; and a second local interconnect connecting the second gate and the first conductive layer therebetween.
By forming the insulating layers and the conductive layers on the first and second gates in such a way, capacitors can be formed on the first and second gates. Herein, by connecting the first gate and the second conductive layer therebetween using the first local interconnect, and connecting the second gate and the first conductive layer therebetween using the second local interconnect, capacitances of the respective capacitors can be added to a storage node. Furthermore, with the capacitors formed on the first and second gates, respectively, a group of the first conductive layer, the first insulating layer and the first gate and a group of the second conductive layer, the second insulating layer and the second gate can be patterned using respective common masks. With the common masks employed, a prescribed overlapping area between layers can be ensured, whereby a variation in capacitance added to a storage node can be reduced.
A semiconductor memory device of the present invention includes: word lines; and a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of the first conductivity type, the three being arranged in each memory cell in an extending direction of each word line, wherein the first access MOS transistor and the first driver MOS transistor are formed in the first well, the first and second load MOS transistors are formed in the second well region and the second access MOS transistor and the second driver MOS transistor are formed in the third well region.
By adopting a layout as described above, a layout of an active layer and a gate can be made to assume a simple shape close to a straight line and a memory cell area can be reduced. Accordingly, a variation in capacitance added to a storage node can be decreased while down-sizing a memory cell area.
The first and second gates and the first and second conductive layers each preferably include a polysilicon layer. In this case, the first and second insulating layers are each formed between polysilicon layers.
By adopting such a construction and process, the fabrication process for DRAM (Dynamic Random Access Memory) which has been established based on proven historical records can be applied in a fabrication process for semiconductor memory devices of the present invention, which allows for easy formation of a large capacitance in a small area.
The first and second conductive layers each may be of a structure including a polysilicon layer and a silicide layer formed on the polysilicon layer. Alternatively, the first and second conductive layers each may be of a structure including a layer including metal. By adopting such structures, the first and second conductive layers can be of a low resistance.
The first and second access MOS transistors have respective gates formed by directly stacking an upper conductive layer corresponding to the first and second conductive layer on a lower conductive layer corresponding to the first and second gate.
With such a structure, it is prevented from occurring that the gates of the first and second access MOS transistors are added with respective unnecessary capacitances while lowering resistances of the gates of the first and second access MOS transistors. That is, there arises no necessity to adopt a special method by which the first and second transistors are operated with coupling capacitances.
A semiconductor memory device of the present invention includes: a memory cell region in which said memory cells are formed; and a peripheral circuit region in which a peripheral circuit performing control of operation of memory cells is formed, wherein MOS transistors are formed in the peripheral circuit region. Herein, gates of the MOS transistors in the peripheral circuit region each preferably have the same structure as each of the first and second access MOS transistors.
With the same gate structure adopted, the MOS transistors in the peripheral circuit region and the first and second access MOS transistors can perform ordinary operations.
The first gate has a first portion lacking the first conductive layer thereon and the first portion extends onto a drain of the second load MOS transistor; the second gate has a second portion lacking the second conductive layer thereon and the second portion extends onto a drain of the first load MOS transistor; the first local interconnect is electrically connected to the first portion and the second conductive layer through a first contact hole extending between the first portion and the second conductive layer; and the second local interconnect is electrically connected to the second portion and the first conductive layer through a second contact hole extending between the second portion and the first conductive layer.
As described above, the first and second conductive layers are selectively removed to form the first and second portions and contact sections are formed on the portions, whereby, the contact sections can be formed without increasing an area of a memory cell. Moreover, since the contact sections have only to be formed in the first and second conductive. layers, almost no need arises that an area of a memory cell is increased. Therefore, a capacitance can be added to a storage node without increasing an area of a memory cell.
It is preferable that the first contact hole reaches the second conductive layer locating between the second driver MOS transistor and the second load MOS transistor and the second contact hole reaches the first conductive layer locating between the first driver MOS transistor and the first load MOS transistor. With such a structure adopted, it is prevented from occurring that damage caused by formation of a contact hole affects transistors.
The semiconductor memory device is preferably formed on a semiconductor layer formed on a substrate with an insulating layer interposing therebetween. Like this structure, by adopting an SOI (Silicon On Insulator) structure, soft error resistance can be improved. Besides, a peripheral circuit can also be operated at high speed, and a leakage current can also be reduced.
A fabrication process for a semiconductor memory device relating to the present invention is for a semiconductor memory device including memory cells each having first and second access MOS transistors; first and second driver MOS transistors; and first and second load MOS transistors, and includes the steps of: forming a first conductive layer for forming gates of the first and second access MOS transistors, gates of the first and second driver MOS transistors and gates of the first and second load MOS transistors on a memory cell region with a first insulating layer interposing between the gates and the memory cell region; forming a second insulating layer on the first conductive layer; removing the second insulating layer located on gate forming regions of the first and second access MOS transistors; forming a second conductive layer so as to cover the first conductive layer and the second insulating layer; forming a first mask layer on the second conductive layer to pattern the second conductive layer using the first mask layer; and forming a second mask layer on the first mask layer to pattern the second insulating layer and the first conductive layer using the first and second mask layers, respectively.
As described above, by patterning the second conductive layer, the second insulating layer and the first conductive layer using the first and second mask layers formed on the second conductive layer, there can be formed not only the gates of the respective MOS transistors but also capacitors on the gates of the driver MOS transistor gates and on the gates of the load MOS transistors. In this case, since the second conductive layer is formed after removing the second insulating layer located on the gates of the access MOS transistors, the gates of the access MOS transistors can be formed with two conductive layers, stacked together, and electrically connected to each other, which exerts an effect as described above. Moreover, since a portion covered by the second mask can be sure to be left behind, a prescribed overlapping area can be ensured between the first and second conductive layers, and the second insulating layer. Thereby, a variation in capacitance added to a storage node can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will becomes more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.